Data processing devices and systems are used in myriad applications which touch virtually every aspect of life. FIG. 1 illustrates at 10 part of a conventional data processing system including a CPU or microprocessor 11 and an external memory 13 such as, for example, SRAM or DRAM. In response to a request from the microprocessor 11, the external memory 13 provides the CPU 11 with an N-byte burst of data, which data is transmitted to the CPU 11 via bus 15. The desired portion of the N-byte data burst is input to the core 17 of CPU 11, and the entire N-byte data burst is stored in an N-byte wide cache 19.
FIG. 2 illustrates at 21 part of another conventional CPU. The CPU of FIG. 2 includes a core 23 and a K-byte wide cache 25, where K is less than N. The CPU of FIG. 2 thus could not be used in place of the CPU of FIG. 1, because the K-byte wide cache 25 of FIG. 2 is not wide enough to accommodate the N-byte bursts received from external memory 13 in FIG. 1.
It is therefore desirable to provide improvements which permit the CPU architecture of FIG. 2 to accommodate the N-byte data bursts received from the external memory 13 in the data processing system of FIG. 1.
According to the present invention, a buffer is provided to accommodate all bytes of an external memory burst which cannot be accommodated by the cache of the CPU.